EP2S90F1020C5N

EP2S90F1020C5N Specifications

Manufacturer: Intel (formerly Altera)
Part Number: EP2S90F1020C5N
Product Type: FPGA (Field Programmable Gate Array)
Family: Stratix II
Logic Elements: 90,960
Embedded Memory: 4.1 Mbits
DSP Blocks: 96 (18×18 multipliers)
Package / Case: 1020-Ball Flip-Chip FBGA
Speed Grade: -5
Core Voltage: 1.2 V
I/O Voltage: 1.5 V, 1.8 V, 2.5 V, 3.3 V
I/O Pins: 768
Clock Management: Up to 12 PLLs
Mounting Type: Surface Mount
Operating Temperature Range: 0°C to +85°C
RoHS Status: RoHS Compliant

Key Features

The EP2S90F1020C5N is a high-performance FPGA built on Intel’s Stratix II architecture, delivering over 90,000 logic elements in a single device. It integrates advanced clock management, high-density memory blocks, and embedded DSP functionality into a 1020-ball flip-chip BGA. Supporting up to 768 user I/Os, it enables wide data interfacing for complex designs. Its flexible I/O voltage compatibility allows integration into a range of systems without the need for external level shifting. Additionally, the architecture is optimized for power efficiency while still enabling performance across data-intensive workloads. The FPGA also supports dynamic reconfiguration, which benefits systems that demand flexible logic updates or partial reprogramming.

Applications

Baseband signal processing in 4G and 5G macrocell radios
Digital beamforming in phased array radar systems
Protocol bridging and aggregation in data center switches
Real-time imaging pipelines in medical ultrasound systems
Accelerated math functions in financial algorithm platforms

Product Overview

The EP2S90F1020C5N offers a scalable platform for designers developing performance-sensitive logic and signal processing solutions. It belongs to the Stratix II family, which is built for high-speed operations with enhanced logic and DSP capabilities. With nearly 91,000 logic elements, 4.1 Mbits of on-chip RAM, and a rich DSP fabric, this FPGA handles complex processing workloads with efficiency. Furthermore, its multiple PLLs and extensive clock routing offer low-jitter timing control across various domains. Designed for flexibility and speed, this FPGA supports large I/O expansion and multi-protocol interfaces without compromising signal integrity or thermal margins.

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